Computer Organization and Architecture Designing for Performance – William Stallings – 10th Edition

Foreword
Preface
About the Author
PART ONE INTRODUCTION
Chapter 1 Basic Concepts and Computer Evolution
1.1 Organization and Architecture
1.2 Structure and Function
1.3 A Brief History of Computers
1.4 The Evolution of the Intel x86 Architecture
1.5 Embedded Systems
1.6 Arm Architecture
1.7 Cloud Computing
1.8 Key Terms, Review Questions, and Problems
Chapter 2 Performance Issues
2.1 Designing for Performance
2.2 Multicore, Mics, and GPGPUs
2.3 Two Laws that Provide Insight: Ahmdahl’s Law and Little’s Law
2.4 Basic Measures of Computer Performance
2.5 Calculating the Mean
2.6 Benchmarks and Spec
2.7 Key Terms, Review Questions, and Problems
PART TWO THE COMPUTER SYSTEM
Chapter 3 A Top-Level View of Computer Function and Interconnection
3.1 Computer Components
3.2 Computer Function
3.3 Interconnection Structures
3.4 Bus Interconnection
3.5 Point-to-Point Interconnect
3.6 PCI Express
3.7 Key Terms, Review Questions, and Problems
Chapter 4 Cache Memory
4.1 Computer Memory System Overview
4.2 Cache Memory Principles
4.3 Elements of Cache Design
4.4 Pentium 4 Cache Organization
4.5 Key Terms, Review Questions, and Problems
Appendix 4A Performance Characteristics of Two-Level Memories
Chapter 5 Internal Memory
5.1 Semiconductor Main Memory
5.2 Error Correction
5.3 DDR DRAM
5.4 Flash Memory
5.5 Newer Nonvolatile Solid-State Memory Technologies
5.6 Key Terms, Review Questions, and Problems
Chapter 6 External Memory
6.1 Magnetic Disk
6.2 RAID
6.3 Solid State Drives
6.4 Optical Memory
6.5 Magnetic Tape
6.6 Key Terms, Review Questions, and Problems
Chapter 7 Input/Output
7.1 External Devices
7.2 I/O Modules
7.3 Programmed I/O
7.4 Interrupt-Driven I/O
7.5 Direct Memory Access
7.6 Direct Cache Access
7.7 I/O Channels and Processors
7.8 External Interconnection Standards
7.9 IBM zEnterprise EC12 I/O Structure
7.10 Key Terms, Review Questions, and Problems
Chapter 8 Operating System Support
8.1 Operating System Overview
8.2 Scheduling
8.3 Memory Management
8.4 Intel x86 Memory Management
8.5 Arm Memory Management
8.6 Key Terms, Review Questions, and Problems
PART THREE ARITHMETIC AND LOGIC
Chapter 9 Number Systems
9.1 The Decimal System
9.2 Positional Number Systems
9.3 The Binary System
9.4 Converting Between Binary and Decimal
9.5 Hexadecimal Notation
9.6 Key Terms and Problems
Chapter 10 Computer Arithmetic
10.1 The Arithmetic and Logic Unit
10.2 Integer Representation
10.3 Integer Arithmetic
10.4 Floating-Point Representation
10.5 Floating-Point Arithmetic
10.6 Key Terms, Review Questions, and Problems
Chapter 11 Digital Logic
11.1 Boolean Algebra
11.2 Gates
11.3 Combinational Circuits
11.4 Sequential Circuits
11.5 Programmable Logic Devices
11.6 Key Terms and Problems
PART FOUR THE CENTRAL PROCESSING UNIT
Chapter 12 Instruction Sets: Characteristics and Functions
12.1 Machine Instruction Characteristics
12.2 Types of Operands
12.3 Intel x86 and ARM Data Types
12.4 Types of Operations
12.5 Intel x86 and ARM Operation Types
12.6 Key Terms, Review Questions, and Problems
Appendix 12A Little-, Big-, and Bi-Endian
Chapter 13 Instruction Sets: Addressing Modes and Formats
13.1 Addressing Modes
13.2 x86 and ARM Addressing Modes
13.3 Instruction Formats
13.4 x86 and ARM Instruction Formats
13.5 Assembly Language
13.6 Key Terms, Review Questions, and Problems
Chapter 14 Processor Structure and Function
14.1 Processor Organization
14.2 Register Organization
14.3 Instruction Cycle
14.4 Instruction Pipelining
14.5 The x86 Processor Family
14.6 The ARM Processor
14.7 Key Terms, Review Questions, and Problems
Chapter 15 Reduced Instruction Set Computers
15.1 Instruction Execution Characteristics
15.2 The Use of a Large Register File
15.3 Compiler-Based Register Optimization
15.4 Reduced Instruction Set Architecture
15.5 RISC Pipelining
15.6 MIPS R4000
15.7 SPARC
15.8 RISC versus CISC Controversy
15.9 Key Terms, Review Questions, and Problems
Chapter 16 Instruction-Level Parallelism and Superscalar Processors
16.1 Overview
16.2 Design Issues
16.3 Intel Core Microarchitecture
16.4 ARM Cortex-A8
16.5 ARM Cortex-M3
16.6 Key Terms, Review Questions, and Problems
PART FIVE PARALLEL ORGANIZATION
Chapter 17 Parallel Processing
17.1 Multiple Processor Organizations
17.2 Symmetric Multiprocessors
17.3 Cache Coherence and the MESI Protocol
17.4 Multithreading and Chip Multiprocessors
17.5 Clusters
17.6 Nonuniform Memory Access
17.7 Cloud Computing
17.8 Key Terms, Review Questions, and Problems
Chapter 18 Multicore Computers
18.1 Hardware Performance Issues
18.2 Software Performance Issues
18.3 Multicore Organization
18.4 Heterogeneous Multicore Organization
18.5 Intel Core i7-990X
18.6 ARM Cortex-A15 MPCore
18.7 IBM zEnterprise EC12 Mainframe
18.8 Key Terms, Review Questions, and Problems
Chapter 19 General-Purpose Graphic Processing Units
19.1 Cuda Basics
19.2 GPU versus CPU
19.3 GPU Architecture Overview
19.4 Intel’s Gen8 GPU
19.5 When to Use a GPU as a Coprocessor
19.6 Key Terms and Review Questions
PART SIX THE CONTROL UNIT
Chapter 20 Control Unit Operation
20.1 Micro-Operations
20.2 Control of the Processor
20.3 Hardwired Implementation
20.4 Key Terms, Review Questions, and Problems
Chapter 21 Microprogrammed Control
21.1 Basic Concepts
21.2 Microinstruction Sequencing
21.3 Microinstruction Execution
21.4 TI 8800
21.5 Key Terms, Review Questions, and Problems
Appendix A Projects for Teaching Computer Organization and Architecture
A.1 Interactive Simulations
A.2 Research Projects
A.3 Simulation Projects
A.4 Assembly Language Projects
A.5 Reading/Report Assignments
A.6 Writing Assignments
A.7 Test Bank
Appendix B Assembly Language and Related Topics
B.1 Assembly Language
B.2 Assemblers
B.3 Loading and Linking
B.4 Key Terms, Review Questions, and Problems
References
Index
Credits